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Features
* Operating Voltage: 5V * Access Time: 30, 45 ns * Very Low Power Consumption * * * * * * * *
- Active: 600 mW (Max) - Standby: 1 W (Typ) Wide Temperature Range: -55C to +125C 400 Mils Width Packages: FP32 and SB32 TTL Compatible Inputs and Outputs Asynchronous No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 QML Q and V with SMD 5962-89598 ESCC with Specification 9301/047
Description
The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits. Utilizing an array of six transistors (6T) memory cells, the M65608E combines an extremely low standby supply current (Typical value = 0.2 A) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The M65608E is processed according to the methods of the latest revision of the MIL PRF 38535 or ESCC 9000.
Rad. Tolerant 128K x 8 5-volts Very Low Power CMOS SRAM M65608E
Rev. 4151M-AERO-07/07
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M65608E
Block Diagram
Pin Configuration
32-lead DIL side-brazed 32-lead Flatpack 400 MILS 400 MILS
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Pin Description
Table 1. Pin Names
Names A0 - A16 I/O0 - I/O7 CS1 CS2 WE OE VCC GND Description Address inputs Data Input/Output Chip select 1 Chip select 2 Write Enable Output Enable Power Ground
Table 2. Truth Table
CS1 H CS2 X W X OE X Inputs/ Outputs Z Mode
Deselect/ Power-down Deselect/ power-down Read Write Output Disable
X L L L Note:
L H H H
X H L H
X L X H
Z Data Out Data In Z
L = low, H = high, X = H or L, Z = high impedance.
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Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential:..........................-0.5V + 7.0V DC input voltage: ..............................GND - 0.5V to VCC + 0.5 DC output voltage high Z state: ........GND - 0.5V to VCC + 0.5 Storage temperature: ..................................... -65C to +150C Output current into outputs (low): .................................. 20 mA Electro statics discharge voltage: ............................... > 2001V (MIL STD 883D method 3015.3)
*NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Military Operating Range
Operating Voltage 5V + 10% Operating Temperature -55C to + 125C
Recommended DC Operating Conditions
Parameter Description Minimum 4.5 0.0 GND - 0.5 2.2 Typical 5.0 0.0 0.0 - Maximum 5.5 0.0 0.8 VCC + 0.5 Unit V V V V
VCC GND VIL VIH Capacitance
Parameter
Supply voltage Ground Input low voltage Input high voltage
Description
Minimum - -
Typical - -
Maximum 8 8
Unit pF pF
Cin(1) Cout(1)
Note:
Input low voltage Output high voltage
1. Guaranteed but not tested.
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DC Parameters
DC Test Conditions Table 3. DC Test Conditions TA = -55C to + 125C; Vss = 0V; VCC = 4.5V to 5.5V
Symbol Description Minimum -1 Typical - Maximum 1 Unit A
IIX (1) IOZ(1) VOL (2) VOH (3)
1. 2. 3.
Input leakage current Output leakage current Output low voltage Output high voltage
-1 - 2.4
- - -
1 0.4 -
A V V
GND < Vin < VCC, GND < Vout < VCC Output Disabled. VCC min. IOL = 8 mA VCC min. IOH = -4 mA.
Consumption
Symbol Description 65608E-30 2 65608E-45 2 Unit mA Value max
ICCSB (1) ICCSB1 (2) ICCOP (3)
1. 2. 3.
Standby supply current Standby supply current Dynamic operating current
300
300
A
max
110
100
mA
max
CS1 > VIH or CS2 < VIL and CS1 < VIL. CS1 > VCC - 0.3V or, CS2 < GND + 0.3V and CS1 < 0.2V. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = GND or VCC, VCC max.
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AC Parameters
AC Test Conditions Input Pulse Levels: ....................................GND to 3.0V Input Rise/Fall Times: ...............................5 ns Input Timing Reference Levels: ................1.5V Output loading IOL/IOH (see Figure 1 and Figure 2)+30 pF AC Test Loads Waveforms
Figure 1
Figure 2
Figure 3
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention chip select CS1 must be held high within VCC to VCC 0.2V or, chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V).
Timing
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Data Retention Characteristics
Parameter Description Minimum 2.0 Typical TA = 25 C - Maximum - Unit V
VCCDR
VCC for data retention Chip deselect to data retention time Operation recovery time Data retention current at 2.0V Data retention current at 3.0V
TCDR
0.0
-
-
ns
TR
TAVAV(1)
-
-
ns
ICCDR1
(2)
-
0.1
150
A
ICCDR2
Notes:
(2)
-
0.2
200
A
1. TAVAV = Read Cycle Time 2. CS1 = VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at VCC = 2V.
Write Cycle
Symbol Parameter 65608-30 30 0 22 18 22 22 8 22 0 0 0 65608-45 45 0 35 20 35 35 15 35 0 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns Value min min min min min min max min min min min
TAVAW TAVWL TAVWH TDVWH TE1LWH TE2HWH TWLQZ TWLWH TWHAX TWHDX TWHQX
Note:
Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 high to write end Write low to high Z(1) Write pulse width Address hold from to end of write Data hold time Write high to low Z(1)
1. Parameters guaranteed, not tested, with output loading 5 pF.
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Read Cycle
Symbol Parameter 65608-30 30 30 5 30 3 15 30 3 15 12 0 8 65608-45 45 45 5 45 3 20 45 3 20 15 0 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns Value min max min max min max max min max max min max
TAVAV TAVQV TAVQX TE1LQV TE1LQX TE1HQZ TE2HQV TE2HQX TE2LQZ TGLQV TGLQX TGHQZ
Note:
Read cycle time Address access time Address valid to low Z(1) Chip-select1 access time CS1 low to low Z(1) CS1 high to high Z(1) Chip-select2 access time CS2 high to low Z(1) CS2 low to high Z(1) Output Enable access time OE low to low Z(1) OE high to high Z(1)
1. Parameters Guaranteed, not tested, with output loading 5 pF.
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Write Cycle 1 WE Controlled, OE High During Write
Write Cycle 2 WE Controlled, OE Low
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Write Cycle 3 CS1 or CS2, Controlled
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
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Read Cycle 1
Read Cycle 2
Read Cycle 3
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Ordering Information
Part Number Temperature Range
(1)
Speed 30 ns 30 ns 30 ns 30 ns 45 ns 45 ns 30 ns 30 ns 45 ns 45 ns 30 ns 30 ns 45 ns 45 ns 30 ns 30 ns
Package SB32.4 FP32.4 SB32.4 FP32.4 SB32.4 FP32.4 SB32.4 FP32.4 SB32.4 FP32.4 SB32.4 FP32.4 SB32.4 FP32.4 Die Die
Flow Engineering Samples Engineering Samples QML Q QML Q QML Q QML Q QML V QML V QML V QML V ESCC ESCC ESCC ESCC Engineering Samples QML V
MMC9-65608EV-30-E MMDJ-65608EV-30-E 5962-8959847QZC 5962-8959847QTC 5962-8959818QZC 5962-8959818QTC 5962-8959847VZC 5962-8959847VTC 5962-8959818VZC 5962-8959818VTC 930104703 930104704 930104701 930104702 MM065608EV-30-E 5962-8959847V6A
Note:
25C 25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C1 25C -55 to +125C
1. Contact Atmel for availability.
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Package Drawings
32-lead Flat Pack 400 Mils
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M65608E
Package Drawings
32-lead Side Braze 400 Mils
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M65608E
Document Revision History
Changes from Rev L. 04/07 to Rev. M 07/07
1. Change in "Consumption" on page 5. ICCOP.
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4151L-AERO-04/07 /xM

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